1. Field of the Invention
The present invention generally relates to a circuit design method for designing an integrated circuit, a circuit design system, and a program for causing a computer to perform a circuit design, and more particularly to the circuit design method, the circuit design system, and the program for causing the computer to perform the circuit design, in which instead of increasing a short TAT (Turn Around Time) and a chip surface area, a cross-talk noise can be suppressed.
2. Description of the Related Art
In a conventional circuit design technology of an integrated circuit, when a cross-talk noise error is corrected, in order to eliminate a cross-talk noise error, circuits are re-arranged and re-wired by additionally providing buffers and spaces (buffering and spacing).
Moreover, Japanese Laid-open Patent Application No. 59-3949 offers to arrange a level shift element capable of changing a threshold voltage of an input buffer gate.
However, in the conventional circuit design method, in a case of conducting the buffering, a quantity of buffers is increased. Also, in a case of performing the spacing, an extra space area is increased. As a result, a chip size is increased. Moreover, in a conventional modification of a chip layout, the circuits are repeatedly arranged and wired until the cross-talk error is eliminated. Once the circuits are re-arranged and re-wired, it is required to extract a resistance value and a capacitance value again, and to perform a delay calculation again. Accordingly, an increase of a man-hour is caused. Also, in this case, a new error can be detected, and also, various increases related to a gate size (an increase of an arrangement area and an increase of a power supply) are caused.
In addition, in a configuration of the integrated circuit disclosed in the Japanese Laid-open Patent Application No. 59-3949, there are the same problems in a case of a re-arrangement and a re-wiring by arranging the level shift element.